Open Topics for Theses

This page contains a list of currently avalibale thesis topics at our chair. This topics can apply for undergraduated student topics (e.g. FIN-SMK, programming projects, et.c) and for bachelor and master's theses.

If you do not find a fitting topic, but have a strong interest in doing you thesis at our chair, do not hesitate to contact Prof. Ortmeier via our secretary Fr. Rulf (kronelia.rulf(at)ovgu.de).

Automated Test Model Generation and Evaluation for Model Transformation Verification in Simulink-Based Systems Development

This thesis tackles the challenge of verifying semantic consistency in Simulink model transformations. It proposes an automated method for test model generation, reducing errors and saving time in complex system design

A Comparison of Failure injection Methods for Functional Safety

This thesis investigates the failure injection capabilities of leading Model-Based Systems Engineering (MBSE) tools, focusing on their integration with safety analysis techniques like FTA and FMEA. Through a comparative study, it will benchmark tool performance and provide guidelines for engineers seeking to optimize safety-critical system design.

Formalized Failure Propagation Analysis for Safety-Critical Systems: From SysML/SafeDeML to Automated Safety Verification

The integration of safety analysis into the early stages of system design using Model-Based Systems Engineering (MBSE) is critical for developing trustworthy safety-critical systems. Methodologies like SafeDeML provide a semi-formal way to embed safety artifacts such as faults, failures, and diagnoses directly within SysML models. However, a significant gap remains in translating these annotated models into a formal domain for rigorous, automated analysis of system-wide failure propagation. This thesis proposes the development of a methodology and a corresponding toolchain to automatically derive a formal, compositional analysis model from a SysML system architecture annotated with SafeDeML. The goal is to enable the automated verification of system-level safety goals against failure propagation scenarios originating from component-level faults.

Last Modification: 22.07.2025 -
Contact Person: Webmaster